In a computer system, instructions are typically fetched from a program memory, decoded and supplied to an execution unit where they are executed to run the program stored in the program memory. It is advantageous for such a computer system to be able to support more than one instruction mode. A novel computer system described herein can support three instruction modes.
According to a first instruction mode, during each machine cycle a pair of 16 bit instructions are decoded.
According to a second instruction mode, during each machine cycle two 32 bit instructions are decoded.
According to a third instruction mode, four 32 bit instructions are decoded during each machine cycle.
In practice, a prefetch unit fetches a word from memory having a length of 128 bits. This word can contain eight 16 bit instructions (GP16 mode), four independent 32 bit instructions (GP32) or four interrelated 32 bit instructions (VLIW mode). The four 32 bit instructions in VLIW mode are interrelated in the sense that they have to conform to a certain grammar such that they can be fetched and supplied to the decoder together. The prefetch unit supplies an 128 bit sequence to the decode unit on each machine cycle. However, the decode units should supply to the execution unit decoded outputs only for the instructions to be decoded in that machine cycle.
The aim of the present invention is to provide a decode unit which is simple and power efficient, which can nevertheless accurately supply decoded outputs to the execution unit in accordance with the instruction mode of the computer.